Data storage is an essential requirement for virtually all modern digital electronic systems. Static read/write memory (SRAM) comprises a major part of that function, being relatively easy to integrate into a semiconductor device together with large amounts of logic, thus offering fast access and low power. With the advent of deep sub-micron (DSM) geometry silicon processing, the task of implementing reliable storage whilst simultaneously maintaining low power consumption becomes increasingly problematic, whilst conversely demand rises with the proliferation of battery-powered electronic gadgets requiring progressively larger memories.
The most commonly-used design of SRAM memory cell is the 6-transistor circuit shown in FIG. 1 and consists of a storage element made up of two back-to-back/cross-coupled inverters ([MN1, MP1] and [MN2, MP2]) 11a, 11b, 12a, 12b with access transistors (MA1 and MA2) 16a, 16b which are turned ON by means of a word line control (WL) to form a conducting path between the data storage nodes (N1 and N2) 13, 14 of the cell and the complementary bit lines (BLA and BLB).
A write operation, in which a data value is written to a memory cell, is achieved by forcing a high voltage onto one of BLA or BLB whilst simultaneously forcing a low voltage onto the other, and then driving the word line (WL) high to activate the access path allowing the voltage levels held on the bit lines (BLA and BLB) to overcome the state of the storage element. The word line is then driven low to disconnect the memory cell with its data store held in its new state.
A read operation in which a data value stored in a memory cell is read, is achieved by initially driving both bit lines to a notionally high voltage level before then driving the word line (WL) high. One of either BLA or BLB will then be pulled low through the access devices (MA1 and MA2) by the low voltage side of the storage element. The complementary bit lines are attached to inputs of a sense amplifier (not shown) that is part of the read circuitry which is used when data is read from the memory. A sense amplifier senses the low level signals present on the bit lines which represent the data value (i.e. either a ‘1’ or a ‘0’) stored in a given memory cell, and amplifies the small voltage swing to recognisable logic level so that the data can be interpreted properly by logic outside the memory. The difference in voltage levels between the two bit lines can therefore be sensed by the sense amplifier and used to determine the data value (i.e. ‘1’ or ‘0’). The decision levels representing a ‘1’ and a ‘0’ will have been pre-determined during the circuit design phase and applied by the sense amplifier.
FIG. 2 illustrates a conventional memory unit wherein the memory cells are arranged in a two-dimensional array consisting of horizontal rows and vertical columns. Each memory cell in the array is connected to a word line that runs horizontally across a row of the array and to a pair of bit lines that run vertically within the columns. By convention the word lines are always said to run along the rows of an array of memory cells whilst the bit lines are always said to run down the columns of an array of memory cells, irrespective of the orientation of the array. The word lines are driven by a row decoder that takes an m-bit address and produces 2m word line enable signals. Each pair of bit lines is then driven by a column decoder that takes an n-bit address and produces 2n bit line signals.
In order to reduce delay and power dissipation, a number of different partitioning approaches have been used in which the memory array is partitioned into a number of smaller blocks that can be separately accessed. In particular, it is common for a memory array to be partitioned by the use of divided/hierarchical word lines and divided/hierarchical bit lines.
In a hierarchical word line arrangement, instead of a single word line that runs the complete width of a row of memory cells and connects to each cell in the row, a multi-level structure is used. Effectively, a single word line is broken up into multiple “local word lines”, each of which connects to a group of memory cells in a part of a row of the array. A “global word line” then runs the width of the row and is connected to each of the local word lines in that column via gates/switches.
Similarly, in a hierarchical bit line arrangement in which, instead of a single bit line that runs the complete height of a column of memory cells and connects to each cell in the column, another multi-level structure is used. Effectively, a single bit line is broken up into multiple “local bit lines”, each of which connects to a group of memory cells in a part of a column of the array. A “global bit line” also runs the height of the column, and is connected to each of the local bit lines in that column via an interface circuit. The memory read and write circuits connect to the global bit line, and not directly to the local bit line. During a memory access, only a local bit line in the relevant part of the column is connected to the global bit line.
One crucial part of the design of the 6-transistor memory cell is the drive strength ratios of the NMOS (n-channel metal-oxide semiconductor field effect transistor) pull down transistors (MN1 and MN2), the NMOS access devices (MA1 and MA2) and the PMOS (p-channel metal-oxide semiconductor field effect transistor) pull up devices (MP1 and MP2). In particular, the access devices need to be sufficiently large relative to the pull-up devices to guarantee that the cell state is over-written during a write, but not so large (relative to the pull-down devices) that the cell becomes over-loaded and unstable during a read thereby causing the stored data value to be lost.
The act of reading a 6-transistor memory cell therefore presents its most challenging operating condition for retaining its data whilst the storage elements are loaded via the access devices (i.e. access devices turned on and both bit lines high). With the inevitable degree of random device variability suffered on DSM technologies due to the very small geometry of the individual devices, simultaneously meeting both writability and read stability criteria on all cells in a very large memory (10's of millions of bits) becomes extremely challenging.
In order to alleviate the difficulty of addressing these conflicting requirements simultaneously, an increasingly common practice is to use memory cells that have dedicated read ports, often referred to as read-decoupled memory cells, that provide a path for accessing a memory cell during a read operation that is separate to that used for write operations. FIGS. 3 and 4 illustrate two different examples of read-decoupled memory cells.
FIG. 3 shows an 8-transistor cell design that separates out the write and read paths of the circuit by the addition a single-ended read port. The single-ended read port comprises a data read transistor (MDR) is connected to a storage node (N2) of the memory cell and a read access transistor (MAR) that is controlled by an associated read word line (RWL). The read word line (RWL) is separate/distinct from the word line (WL) that controls access to the memory cell during a write operation. The NMOS data read transistor (MDR) is configured as a pull-down transistor whose gate is connected to the storage node of the memory cell and whose source is connected to ground. The data read transistor (MDR) is connected in series with the NMOS read access transistor (MAR) whose gate is connected to the read word line (RWL) and whose drain is connected to a read bit line (RBL). The read access transistor (MAR) can thereby provide a conducting path between the data storage node (N2) of the cell and the read bit line (RBL). Write operations on this 8-transistor cell design are identical to those for the 6-transistor cell. For reads, however, instead of the write word line (WWL) being driven high, the single read bit line (RBL) is initially pre-charged to a high voltage and then the read word line (RWL) driven high. That enables the data-dependent discharge path from the read bit line (RBL) through the cell to VSS, and so the read bit line (RBL) will either stay high (due to its capacitance) or be pulled low by the cell. The state of the read bit (RBL) line can then be sensed to determine the data value stored in the selected bit. Whilst this example shows a read-decoupled memory cell comprising conventional 6-transistor cell with the addition of one single-ended read port, it is possible to include multiple single-ended read ports within a single cell.
FIG. 4 shows an alternative 8-transistor cell design that separates out the write and read paths of the circuit by the addition a differential/double-ended read port. The differential/double-ended read port comprises a first read access transistor (MAR1) connecting a first storage node (N1) of the memory cell to a first (RBLA) of a pair of complementary read bit lines, and a second read access transistor (MAR2) connecting a second storage node (N2) of the memory cell to a second (RBLB) of the pair of complementary read bit lines. The differential/double-ended read port therefore essentially replicates the access transistors of a conventional 6-transistor cell (i.e. that control the connection of the complementary bit lines to the storage nodes) so that there are separate yet corresponding write and read paths for the cell. As with a conventional 6-transistor cell, during a write operation, the write access transistors (MA1 and MA2) are turned on by means of a write word line to form a conducting path between the data storage nodes (N1 and N2) of the cell and the complementary bit lines (BLA and BLB). Then, during a read operation, the first and second read access transistors (MAR1 and MAR2) are turned on by means of a read word line control (RWL) to form a conducting path between the data storage nodes (N1 and N2) of the cell and the complementary read bit lines (RBLA and RBLB). This design allows the access devices to be sized differently for read and write operations to allow more flexible optimisation, but the internal nodes are still stressed by a read operation.
Conventionally, an SRAM memory performs one access operation (read or write) per cycle (rise and fall) of a clock signal. This, however, requires that the clock signal changes twice per access, while the data lines change at most once per access. When operating at a high bandwidth, system considerations often constrain the frequency at which the clock single can operate. However, it is possible for the memory circuits to operate at multiple data rates, wherein multiple accesses occur within a single cycle of an external clock signal. For example, the memory circuits can be configured to implement access operations on both the rising and falling edges of the external clock such that the data signals operate with the same limiting frequency, thereby doubling the data transmission rate.